Semiconductor devices sometimes have a DLL circuit for delaying an external clock signal supplied from the outside of the semiconductor devices by a desired delay time to generate an internal clock signal. In a synchronous memory, for example, in order to output data in synchronization with an external clock signal, the internal clock signal is generated from the external clock signal, and the timing of outputting the data is synchronized with the internal clock signal. In view of the delay time of a circuit for outputting the data, the internal clock signal is generated to have a phase so that the timing of outputting the data from the synchronous memory matches the rise (or fall) timing of the external clock signal.
Nonpatent Document 1 discloses a typical DLL circuit. FIG. 8 is a schematic diagram of a DLL circuit that is known. The known DLL circuit includes an input buffer 101, a delay selection circuit 102, and a delay synthesis circuit 103. The delay selection circuit 102 includes delay elements 1041 to 104N connected in series, where N is a natural number equal to or more than two, and a selector 105.
An external clock signal CLKEX supplied from an outside of the DLL circuit is input to the input terminal of the input buffer 101. The input buffer 101 reproduces the waveform of the external clock signal CLKEX to generate a clock signal CLK1.
The clock signal CLK1 is input to the input terminal of the delay element 1041 in the first stage of the delay selection circuit 102. The delay elements 1041 to 104N connected in series delay clock signals input to the delay elements 1041 to 140N, respectively, and outputs clock signals T1 to TN from their output terminals, respectively. The delay time of the clock signal Tp with respect to the internal clock signal CLK1, where p is a natural number equal to or less than N, is larger as p increases.
The selector 105 selects two-clock signals FDLO and FDLE output from two adjacent delay elements from among the clock signals T1 to TN output from the output terminals of the delay elements 1041 to 104N, respectively. Of the clock signals FDLO and FDLE, the clock signal FDLE corresponds to the clock signal output from the delay element 1042q in an even-numbered stage, while the clock signal FDLO corresponds to the clock signal output from the delay element 1042q+1 in an odd-numbered stage, where q is a natural number selected so that 2q+1 does not exceed N. The delay synthesis circuit 103 synthesizes the clock signals FDLO and FDLE to generate an internal clock signal CLKIN. The delay synthesis circuit 102 further has a function of finely adjusting its delay time.
The delay time of the known DLL circuit is coarsely adjusted to be close to a desired value by adequately selecting two of the clock signals T1 to TN to generate the clock signals FDLO and FDLE. Further, the delay time of the DLL circuit is accurately adjusted to the desired value by the operation of the delay synthesis circuit 103.
One problem with the known DLL circuit is that the minimum delay time that can be achieved by the DLL circuit (which will be hereinafter simply referred to as the “minimum delay time”) increases when the number of the delay elements 1041 to 104N is increased so as to allow a wide range of adjustment of the delay time. As the number of the delay elements 1041 to 104N is increased, the number of input terminals of the selector 105 also increases. As is well known by a person skilled in the art, as the number of the input terminals of the selector 105 increases, the delay time of the selector 105 increases with it. An increase in the delay time of the selector 105 would increase the minimum delay time of the DLL circuit. A large minimum delay time of the DLL circuit is not desirable since it hinders a faster operation of the semiconductor device into which the DLL circuit is integrated.
It is desirable for the DLL circuit to have a small minimum delay time. It is more preferable that the DLL circuit has the small minimum delay time while allowing the wide range of adjustment of the delay time.
[Nonpatent Document 1]
Tatsuya Matano et al., “A 1 Gb/s/pin 512 Mb DDR2 SDRAM using a digital DLL and a slew-rate-controlled output buffer”, 2002 VLSI Symposium: thesis number 9-1